Technical Papers

The FPGA prototyping system must offer enterprise-wide accessibility ― a complete prototyping platform is one that operates at any functional design stage, with any design size, and across multiple geographical locations. All of these capabilities must be available on demand and remotely-accessible at all times. Such an approach would significantly increase engineering productivity and reduce the end-product's time to market, while increasing its return on investment (ROI), as well as increasing the lifetime ROI of the FPGA prototyping platform itself.

Debugging a single FPGA design is a relatively simple task. However, performing debug operations on a multi-FPGA platform is an extremely long and often labor-intensive process. Manual techniques only allow for debugging one FPGA at a time and traditional tools such as an external logic analyzer or FPGA internal logic analyzer have limitations when it comes to multi-FPGA debug. With manual processes, only gaining insight into the behavior of one FPGA at a time may result in missed design errors or misleading design behavior as it becomes difficult to test the functionality of the design as a whole. The part of a design that resides on a particular FPGA may be bug-free in its compartmentalized form, but when operated within the totality of the design may contain critical errors. External Logic analyzers have a limited number of probes and require designers to pull their probes to the top level so they come out from the FPGAs' I/O pins. Because of these issues, debug has been largely inadequate within the FPGA prototyping process thus leaving debug to be done only through simulation and/or emulation.

SoC design methodology has greatly matured over the past decade and many obstacles have been solved by improved semiconductor technologies, better EDA tools, and new design Servicess. Also thanks to the rapid development of silicon IP industry, designers today can buy most of the design blocks required in an SoC in the market. Nevertheless, putting these IP blocks in an optimal way becomes a key issue, especially when we need to consider system level issues such as performance, bandwidth and power. Moreover, as software content for an SoC continues to enlarge, the ability to co-design software and hardware early becomes a necessity. This whitepaper describes a design methodology that utilizes FPGA-based IP models to create early system prototypes at near real-time speed that allow early software and hardware co-design. Be the first one to the market with the right SoC product by adopting the FPGA-based electronic system level (ESL) methodology.

Increasingly silicon IP vendors are utilizing FPGA prototypes as the vehicles for both pre-sales and post-sales support of their IP cores. FPGA prototypes facilitate IP vendors to allow their potential customers to see and evaluate their IP securely at near real-time speed. The FPGA prototype also can serve as a reference design for customers to speed up their design process after the IP transaction is complete. This whitepaper describes how CAST has selected S2C's TAI Logic Module, a commercial FPGA prototyping tool, to build their H.264 Encoder IP demonstration platform.

Using multiple FPGAs to prototype a large design requires solving a classic problem: the number of signals that must pass between devices is greater than the number of I/Os pins on an FPGA. The classic solution is to use a TDM (Time Domain Multiplexing) scheme that muxes two or more signals over a single wire or pin. This solution is still widely employed, and coupled with the advances in FPGAs, the obstacles to constructing a multi-device prototype are greatly reduced. The latest FPGAs offer advantages such as a very high number of industry-standard I/O, integrated high-speed transceivers, and LVDS signaling.