Early software and/or firmware development on FPGA prototypes, pre-silicon, has become more important as many unforeseen software bugs stem from the complexity of integrating operating system (OS), applications, and hardware. Most projects can't afford to wait until the silicon is back from the foundry to start software validation. An at-speed FPGA prototype allows for many extra months of rigorous software development and software validation at the crucial software-hardware integration stage. In addition, the larger the design, the more system replicates are required increasing development budgets. The low cost of FPGA prototyping systems enables project managers to replicate more platforms to speed up software development.
S2C's advanced Prodigy Prototyping technology allows designers to reach software development much earlier than other prototyping tools. Our off-the-shelf systems are scalable enough to meet the demands of even the largest designs while remaining flexible. S2C's solutions cost much less than building prototyping systems in-house. When compared to emulation, our technology is also much less expensive yet much faster. The time saved by using the industry's highest performing prototyping systems provided by S2C enables designers to focus on adding more differentiation through software development. Validation environments can be quickly built and extended using S2C's vast library of daughter cards. Users can feel secure working with highly reliable technology backed by world-class customer support.
For design teams that would like to fine-tune firmware cores, critical RTOS sessions, or the processor micro-architecture, a soft processor IP is needed. With the soft processor IP inside, the FPGA prototype can provide more visibility, control, and flexibility. On the flip side, integrating the processor IP into the FPGA prototype typically requires multiple FPGAs. As a result, tools designed for multiple-FPGA debugging, such as S2C's prototyping platform is pretty valuable. These tools offer an effective and efficient debug approach for validating SoC designs to provide good visibility to the SoC behavior without sacrificing execution performance.
