Design Stages For Soc / ASIC Application Demands

Classic hardware verification tools such as FPGA prototyping, together with transaction-level testing, are increasingly finding their way into design exploration space for architecture optimization. Read more about these challenges and how S2C technology can help.

The available EDA tools used for IP verification today support a wide range of IP and SoC abstractions during IP development, including ESL modeling, software simulators,verification IP, formal verification, emulation and FPGA prototyping.

In the context of today’s hardware and SoC verification complexities, and considering the high portion of the total SoC development effort that is devoted to verification, it is clear why designers are constantly seeking better ways to include more real-life end-system operation of SoC designs as early as possible in the development process.

Realizing early System Validation is the primary purpose of EDA tools like emulation and FPGA prototyping. With more real system-level inputs, system validation helps to find the bugs not found in the verification stage.

Effective hardware/software co-verification requires running the system & SoC at some minimum operating speed (ranging from megahertz to tens of megahertz), within an accurate representation of the “target” system (if not the actual system itself). Software simulation tools are the workhorse tools for system verification, including software verification.

SoC-based product developers today take advantage of early FPGA prototyping to extend SoC Compatibility Testing to include some, if not all, of the product's software running on the SoC-based hardware before silicon - a testimony to the claim that the primary application of FPGA prototyping today is for early hardware/software co-verification.