Dec 21, 2021 December 7, 2021
Press Contacts:
Christopher Browy
(978) 851-3627
cbrowy@avery-design.com
Tewksbury, MA – December 7, 2021 – Avery Design Systems, a leader in functional verification solutions, today announced the latest in native FPGA speed adapters for PCIe® Gen6 and advanced memory technologies for LPDDR5 and HBM3. The latest offering is a result of a partnership with S2C EDA and its Prodigy Logic Matrix LX2 System for high-performance ASIC/SoC prototyping, and enables system validation of the latest data center, NVMe and embedded storage, and AI/ML SoC designs that incorporate the latest high speed interconnect and memory technologies.
"Avery speed adapters accelerate software development, hardware verification and system validation by enabling FPGA prototypes to be integrated with native system platforms to allow validation to be performed at actual system run speeds. This approach overcomes the inherent performance limitations of multi-FPGA representations of System SoCs and that lack support for latest generation of PCIe or memory technologies,” said Chris Browy, VP sales and marketing of Avery." By partnering with S2C we address the ever-increasing complexity and performance requirements in large-scale SoC designs with a solution that provides accurate and timely verification methodologies.”
"FPGA prototyping, in essence, is about high-performance validation. The high-performance quality not only accelerates the design cycle but also enables hardware and software bugs to be caught through the interaction with real-world data,” said Ying Chen, VP sales and marketing of S2C. “The Logic Matrix LX2 is a high-density FPGA prototyping platform with eight Xilinx VU19P FPGAs designed to address the needs for both capacity and performance in complex SoC designs. By partnering with Avery, our customers can now easily validate against the latest generations of PCIe and memory interfaces.”
Avery Memory Speed Adaptor highlights:
Supports HBM2E, HBM3, DDR4, LPDDR4, LPDDR5 DFI 5.0 interfaces to SoC (DUT)
Frequency ratioing of 1:1, 1:2, and 1:4
Debugging log file through UART interface controlled by MCU
Supports Xilinx FPGAs and leverages low cost DDR4 daughter card memory
Includes simulation, synthesis and timing scripts
Avery PCIe Speed Adapter highlights:
Connect SoC prototype PCIe Endpoint (EP) to a full speed PCIe Root Complex (RC)/host server platform slot
Configure RC and EP configurations independently
-EP interface compliant with PCIe Gen3 thru Gen6
-RC interface compliant with native PC host
-Ex: (EP 16x, PIPE 64bit, Gen 4.0) to (RC 4x, PIPE 32bit, Gen 3.0)
Multiple lane widths – of x4, x8, and x16
Supports multiple PIPE Data widths and PIPE rates
Original mode, SERDES architecture, Low pin count interfaces
Frequency scaling factor of emulated device down to 1/64
Power management state of L0
Physical layer initialization, including equalization
Avery supports a spectrum of system-level validation and hardware accelerated solutions that complements its full line of leading SystemVerilog/UVM Verification IP
Virtual host and embedded platform co-simulation using QEMU and Arm Fast Models
SimAccel co-emulation software tools and system IP targeted to any Xilinx FPGA boards
Advanced Accelerated VIPs for PCIe, CXL, Arm AMBA AXI, AHB, APB, embedded monitor
Speed adapters support native system integration
About Avery:
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers.
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