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Virtex UltraScale Prodigy Logic System Configuration Table

Virtex UltraScale Prodigy Logic System Configuration Table

QuadDualSingle
Estimated ASIC Gates（M）1206030
FPGAs4 * XCVU4402 * XCVU4401 * XCVU440
System Logic Cells22,164K11,082K5,541K
FPGA Internal Memory (Mb)354.4 Mbits177.2 Mbits88.6 Mbits
DSP Slices11,5205,7602,880
External User I/Os4,7362,3681,184
SerDes Transceivers176 GTH88 GTH44 GTH
DDR4 SO-DIMM421
Prodigy Connectors32168
PGT Connectors842
DM Connectors421
DatasheetDownloadDownloadDownload


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What type of chip are you designing
What is the capacity of the ASIC gate included in the design?
5 million-20 million
20 million-50 million
50 million-100 million
100 million-1 billion
More than 1 billion
Which FPGA do you prefer to use?
Xilinx VU440
Xilinx KU115
Xilinx VU19P
Xilinx VU13P
Xilinx VU9P
AMD VP1802
AMD VP1902
Intel S10-10M
Intel S10-2800
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Single FPGA
Dual FPGA
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Segmentation tool
Multiple FPGA debugging tools
Co-modeling tool (allows large amounts of data to interact between FPGA and PC host)
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6-12 months
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